1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a method of reducing capacitance of interconnect.
2. Discussion of the Related Art
In 1965, Gordon Moore first observed that the number of transistors per unit area on a chip appeared to double approximately every 18 months. Ever since then, the semiconductor industry has managed to introduce new designs and processes on schedule to deliver the improvement in device density projected by the so-called Moore""s Law. In particular, major enhancements in optics and photolithography have reduced the critical dimension (CD) that can be successfully patterned in the features on a chip. At the same time, significant improvements in doping, deposition, and etch have decreased the concentration, depth, and thickness that can be precisely achieved across the chip.
The transistors in a chip are formed in a semiconductor material on a substrate, such as a wafer. The transistors are then wired with multiple layers of interconnects. The interconnects are formed from an electrically conducting material and are isolated by an electrically insulating material. The switching performance of the transistors depends on the resistance-capacitance (RC) product delay in the interconnects.
Thus, what is needed is a method of reducing capacitance of interconnect.